Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other nonvolatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. One important dielectric material for the fabrication of the EEPROM is an oxide-nitride-oxide (ONO) structure. During programming, electrical charge is transferred from the substrate to the silicon nitride layer in the ONO structure. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer and become trapped in the silicon nitride layer. Electrons are trapped near the drain region because the electric fields are the strongest near the drain.
A Flash device that utilizes the ONO structure is a Metal-Oxide-Nitride-Oxide-Silicon (MONOS) cell. A problem exists with known MONOS cell fabrication techniques in that a thickness of a bit-line oxide layer is difficult to control which causes unpredictable MONOS cell performance. If the thickness of the bit-line oxide layer is not accurately formed, charge cannot be adequately stored within the ONO structure.
A problem occurs in that even a 5 to 10 angstrom variation in the thickness of the ONO structure's lower oxide layer can adversely affect the total amount of implanted arsenic. Thereafter, during the bit-line oxidation process, the amount of implanted arsenic affects the rate of oxidation of the bit-line oxide layer. In particular, a heavily doped arsenic implant enhances the oxidation rate. The variation of the arsenic concentration causes a twenty percent variation, or more, in the thickness of the bit-line oxidation layer. The variation in the bit-line oxidation layer produces unpredictable MONOS cell performance.
Another problem exists with known MONOS fabrication techniques in that the quality and cleanliness of the ONO structure cannot be guaranteed during the fabrication process of the transistor. One reason they cannot be guaranteed is that during production of the MONOS type cell, the ONO layer is subjected to repeated photoresist coatings and cleanings, for example, during boron and arsenic implants. To effectively remove the resist layer, the top oxide layer should be aggressively cleaned so that an organic residue of the resist material does not contaminate the top oxide of the ONO structure. Resist material remaining on the top oxide layer of the ONO structure can adversely affect the connection between the top oxide layer and an overlying polycrystalline silicon layer of the MONOS cell which degrades performance of the cell. According to known MONOS type cell structures, however, cleaning cannot be accomplished with an aggressive acid, such as hydrofluoric acid, since the aggressive acid can degrade the top oxide layer of the ONO structure.
Therefore, while recent advances in MONOS cell technology have enabled memory designers to improve MONOS cells, numerous challenges exist in the fabrication of material layers within these devices. In particular, a fabrication process of MONOS cells should accommodate precise control of the thickness of a bit-line oxide layer. In addition, the fabrication process should ensure a high quality ONO structure. Accordingly, advances in MONOS cell fabrication technology are necessary to control bit-line oxide layer fabrication and insure high quality MONOS cell devices.